1. Field of the Invention
The present invention relates to a process for measuring the depth of a source and drain, and more particularly to a process for measuring the depth of a source and drain in a DRAM by measuring resistances of the buried strap between the trench capacitor and transistor at different depths.
2. Description of the Prior Art
Presently, dynamic random access memory (DRAM) is widely used. Generally, a DRAM cell includes a transistor and a capacitor. FIG. 1 shows a circuit diagram of a DRAM cell, in which a drain of an NMOS transistor 10 is connected to a storage electrode of a capacitor 20, a gate of the NMOS transistor is connected to a word line (WL), and a source is connected to a bit line (BL). In addition, an opposed electrode of the capacitor is connected to a constant voltage source. A dielectric layer is located between the storage electrode and opposed electrode. The NMOS transistor acts as a switch to control the charged or discharged state of the capacitor, thus generating the logic level of memory cell.
In the DRAM manufacturing process, a two-dimensional capacitor called a planar-type capacitor is mainly used for a conventional DRAM having a storage capacity less than 1M (mega=million) bits. In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on the main surface of a semiconductor substrate, and thus the main surface is required to have a large area. This type of a memory cell is therefore not suited to a DRAM having a high degree of integration.
For a highly integrated DRAM, such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, such as a stacked-type or a trench-type capacitor, has been introduced. With stacked-type or trench-type capacitors, it has been made possible to obtain a larger memory within a similar volume. In the trench capacitor manufacturing process, insulator (such as silicon oxide/silicon oxynitride or silicon oxide/silicon oxynitride/silicon oxide) and conductor (such as heavily N-doped polysilicon) are formed by many times of deposition and etching to complete the structure. Generally, first, a photoresist mask is formed on a semiconducting substrate. The photoresist layer and semiconducting substrate are then etched to form a trench. Next, a storage electrode layer and a dielectric layer are successively formed in the trench. Finally, conducting material is filled in the trench to complete the trench capacitor.
In L. Nesbit, et al., “A 0.6 μm 256 Mb Trench DRAM Cell With Self-aligned Buried Strap (BEST)”, 1993 IEDM, pp. 627-630, 1993, it is described a process for fabricating a trench capacitor in a DRAM cell.
In the DRAM manufacturing process, if the depth of source and drain does not reach the desired depth, the breakdown voltage of DRAM cell is decreased. Consequently, when the voltage applied to the gate has not reach the predetermined voltage, the DRAM cell is undesirably switched on. However, there is no effective way to measure the depth of source and drain until now.